1. Technical Field
The present invention relates to circuit optimization in general, and in particular to methods for performing post-synthesis circuit optimization on an integrated circuit design.
2. Description of Related Art
Generally speaking, an increase in variability of key process parameters, such as effective channel length (Leff) and threshold voltage (Vth), can significantly impact the design and optimization of integrated circuits in the nanometer regime. The increase in variability can be attributed to many factors, such as manufacturing control problems, emergence of new systematic variation-generating mechanisms, etc. But the most important factor that causes an increase in variability is the increase in fundamental atomic-scale randomness such as variations in the number of dopants in transistor channels.
Low-power devices are vulnerable to process variability because devices with low Vth tend to exhibit larger sensitivity to variations. On the other hand, high-power devices are also vulnerable to process variability because they tend to have a very high leakage power, which leads to a larger yield loss in the high-performance bin. In addition, leakage power (or standby power) of a device increases as the geometry of the device decreases.
Because of their effectiveness in leakage power reduction, post-synthesis circuit optimization techniques, such as sizing and dual-Vth allocation, have been widely explored in a deterministic setting. While relying on different implementation strategies, all of the prior art post-synthesis circuit optimization techniques essentially trade slacks of non-critical paths for power reduction by either reducing transistor sizes and gate sizes or setting them to a higher Vth. The present disclosure provides two improved methods for performing post-synthesis circuit optimization on integrated circuit designs.